Altera Forums

Usermode

ptangella42 — Fri, 18 May 2012 20:37:37 GMT

Can anyone please tell me the procedure for entering the usermode, in order to see the status of the CRC_ERROR pin in cycloneii EP2C35.

Thank you in advance

Arria II GX and SDI-HSMC Daughter card

tsprinkle — Fri, 18 May 2012 20:34:33 GMT

Can anyone point me in the right direction or give me some information about developing with the Arria II GX Development Kit and the SDI-HSMC Daughter card? Every thing I see on the internet has the Stratix IV board using the SDI-HSMC daughter card and the DVI-HSMC daughter card with the Arria II board.

Thanks,

Taylor

Verilog Synthesis Q

MarkEverly — Fri, 18 May 2012 20:29:10 GMT

Am bumping into a synthesis problem inside of an always construct. Simplified code is

reg true_or_false[0:9999];
reg a;

always (negedge clk)
begin
if (a <5000)
true_or_false[a] <= 1
else if (a < 10000)
true_or_false[a+5000] <= 1
end

The error I get is "Cannot convert all sets of registers into RAM megafunctions when creating nodes. The resulting number of registers remaining in design exceeds the number of registers in device....."

If I remove the if else construct, no allocations (register/memory/etc) are > 30%.

I'm quite sure I'm violating an HDL paradigm. Could use a little guidance on why and thoughts on how I might implement it correctly.

THNX,
ME

Help starting out with Arria II GX Dev Board and SDI HSMC Daughter card

tsprinkle — Fri, 18 May 2012 20:09:12 GMT

mSGDMA with different write clock and read clocks

eldos — Fri, 18 May 2012 17:44:20 GMT

Hi,

I am using the modular SGDMA (mSGDMA) with the PCIe connected to DDR memories. NIOS processor programs the descriptors. I would like to use different clocks for descriptor programming, for read side and for write side. Is this possible without modifying the mSGDMA source code?

Thanks!

Terasic DE2-115 flash elf

MarkEverly — Fri, 18 May 2012 17:37:10 GMT

Am using Quartus/Eclipse with DE2-115. Can someone provide some guidance on how to compile NIOS based application developed under eclipse so it can be falshed as opposed to loading through the debugger each execution.

Thnx
ME

Terasic DE2-115 Flash programming

MarkEverly — Fri, 18 May 2012 17:24:48 GMT

Altera classes

dedanaan — Fri, 18 May 2012 14:06:20 GMT

Is it possible to become a partner in Altera? I went through training with an instructor and got considerable experience in FPGA. Can I led a course? Where can I turn to this issue?

On board USB Blaster?

de-em — Fri, 18 May 2012 12:55:10 GMT

Hi,
I want to design in a USB Blaster type adaptor on my ARM board so I can test and program the entire system in situ. I have a spare USB port. It sounds like a good idea in principle but is there a reference design somewhere for this? Is the Altera USB Blaster design open source?

Thanks
D

DE2-115: Problem - ISP1362 Does Not Work

Gladion — Fri, 18 May 2012 12:49:58 GMT

Hi guys,

I am using DE2-115 board configured with SOPC file from included DE2-115 CD (DE2_115_NIOS_DEVICE_LED).

I removed all components except the following:
- pll
- jtag_uart
- cpu
- onchip_memory
- sdram
- clock_crossing_io
- timer
- sysid
- usb

I made some changes on the remaining components as below (SOPC screenshot attached):
1. cpu
- enable hardware divide
- reset & exception vector: memory: sdram
- include mmu
- fast TLB miss exception vector: memory: onchip_memory
- include tightly coupled instruction & data master ports
2. onchip_memory
- enable dual port access
- total memory size: 1024 bytes
3. usb
- changed name to ISP1362

This is the content of DTS file generated:

Code:

/*

 * This devicetree is generated by sopc2dts

 * Sopc2dts is written by Walter Goossens 

 * in cooperation with the nios2 community 

 */

/dts-v1/;



/ {

        model = "ALTR,DE2_115_SOPC";

        compatible = "ALTR,DE2_115_SOPC";

        #address-cells = < 1 >;

        #size-cells = < 1 >;



        cpus {

                #address-cells = < 1 >;

                #size-cells = < 0 >;



                cpu: cpu@0x0 {

                        device_type = "cpu";

                        compatible = "ALTR,nios2-11.1";

                        reg = < 0x00000000 >;

                        interrupt-controller;

                        #interrupt-cells = < 1 >;

                        clock-frequency = < 100000000 >;        /* embeddedsw.CMacro.CPU_FREQ type NUMBER */

                        dcache-line-size = < 32 >;        /* embeddedsw.CMacro.DCACHE_LINE_SIZE type NUMBER */

                        icache-line-size = < 32 >;        /* embeddedsw.CMacro.ICACHE_LINE_SIZE type NUMBER */

                        dcache-size = < 2048 >;        /* embeddedsw.CMacro.DCACHE_SIZE type NUMBER */

                        icache-size = < 4096 >;        /* embeddedsw.CMacro.ICACHE_SIZE type NUMBER */

                        ALTR,implementation = "fast";        /* embeddedsw.CMacro.CPU_IMPLEMENTATION type STRING*/

                        ALTR,pid-num-bits = < 8 >;        /* embeddedsw.CMacro.PROCESS_ID_NUM_BITS type NUMBER */

                        ALTR,tlb-num-ways = < 16 >;        /* embeddedsw.CMacro.TLB_NUM_WAYS type NUMBER */

                        ALTR,tlb-num-entries = < 256 >;        /* embeddedsw.CMacro.TLB_NUM_ENTRIES type NUMBER */

                        ALTR,tlb-ptr-sz = < 8 >;        /* embeddedsw.CMacro.TLB_PTR_SZ type NUMBER */

                        ALTR,has-div;        /* embeddedsw.CMacro.HARDWARE_DIVIDE_PRESENT type NUMBER*/

                        ALTR,has-mul;        /* embeddedsw.CMacro.HARDWARE_MULTIPLY_PRESENT type NUMBER*/

                        ALTR,reset-addr = < 0xc0000000 >;        /* embeddedsw.CMacro.RESET_ADDR type NUMBER */

                        ALTR,fast-tlb-miss-addr = < 0xc9001000 >;        /* embeddedsw.CMacro.FAST_TLB_MISS_EXCEPTION_ADDR type NUMBER */

                        ALTR,exception-addr = < 0xc0000020 >;        /* embeddedsw.CMacro.EXCEPTION_ADDR type NUMBER */

                }; //end cpu@0x0 (cpu)

        }; //end cpus



        memory@0 {

                device_type = "memory";

                reg = < 0x00000000 0x08000000

                        0x09001000 0x00000400 >;

        }; //end memory@0



        sopc@0 {

                ranges;

                #address-cells = < 1 >;

                #size-cells = < 1 >;

                device_type = "soc";

                compatible = "ALTR,avalon", "simple-bus";

                bus-frequency = < 100000000 >;



                clock_crossing_io: bridge@0x8000000 {

                        compatible = "ALTR,avalon-11.1", "simple-bus";

                        reg = < 0x08000000 0x00000040 >;

                        #address-cells = < 1 >;

                        #size-cells = < 1 >;

                        ranges = < 0x00000000 0x08000000 0x00000020

                                0x00000020 0x08000020 0x00000008 >;



                        timer: timer@0x0 {

                                compatible = "ALTR,timer-11.1", "ALTR,timer-1.0";

                                reg = < 0x00000000 0x00000020 >;

                                interrupt-parent = < &cpu >;

                                interrupts = < 0 >;

                                clock-frequency = < 10000000 >;

                        }; //end timer@0x0 (timer)



                        sysid: sysid@0x20 {

                                compatible = "ALTR,sysid-11.1", "ALTR,sysid-1.0";

                                reg = < 0x00000020 0x00000008 >;

                        }; //end sysid@0x20 (sysid)

                }; //end bridge@0x8000000 (clock_crossing_io)



                jtag_uart: serial@0x9001410 {

                        compatible = "ALTR,juart-11.1", "ALTR,juart-1.0";

                        reg = < 0x09001410 0x00000008 >;

                        interrupt-parent = < &cpu >;

                        interrupts = < 1 >;

                }; //end serial@0x9001410 (jtag_uart)



                pll: clock@0x9001400 {

                        compatible = "ALTR,pll-11.1", "ALTR,pll-1.0";

                        reg = < 0x09001400 0x00000010 >;

                }; //end clock@0x9001400 (pll)



                ISP1362: isp1362@0x9001418 {

                        compatible = "nxp,isp1362-1.0", "nxp,usb-isp1362";

                        reg = < 0x09001418 0x00000004

                                0x0900141C 0x00000004

                                0x09001420 0x00000004

                                0x09001424 0x00000004 >;

                        interrupt-parent = < &cpu >;

                        interrupts = < 2 3 >;

                }; //end isp1362@0x9001418 (ISP1362)

        }; //end sopc@0



        chosen {

                bootargs = "debug console=ttyAL0,115200";

        }; //end chosen

};

I made kernel configuration as below:
- platform options
=> enable MULX instruction
=> enable DIV instruction
- device driver
=> SCSI device support
=> SCSI disk support
=> USB support
=> Support for host-side USB
=> USB device filesystem
=> ISP1362 HCD support
=> USB mass storage support
- File Systems
=> Ext3 journalling file system support
=> DOS/FAT/NT Filesystems
=> MSDOS fs support
=> VFAT (Windows-95) fs support
=> Native language support
=> codepage 437
=> NLS ISO 8859-1

I successfully made the image and load into DE2-115 board, but there is where problem occurs:

Condition #1.
If I exclude isp1362 in both sopc & kernel configuration, nios2-linux starts up normally, but with garbage characters occasionally displayed when starting up nios2-linux.

Condition #2.
If I include isp1362 in both sopc & kernel configuration, it is downloaded to the board and verified successfully, but then just hang at there, nothing more comes out in nios2-terminal, nios2-linux fails to start up.

Any advice regarding this matter? Thanks!

Regards,
Gladion

Attached Images

	sopc.jpg (29.7 KB)
	condition1.jpg (42.0 KB)
	condition2.jpg (29.6 KB)

JTAG chain with Cyclone V, MAX V, and Texas Instruments AM3559.

rsribeiro — Fri, 18 May 2012 11:54:22 GMT

Hi

My board will have three JTAG devices: Cyclone V, MAX V, and Texas Instruments AM3559.
I would like to make a JTAG chain with these 3 devices. Will it work?
I have seen that this chain is possible by JTAG definition. Some forum answers to use "JTAG BYPASS" configuration...
But could there be a development tools for these devices that does not support it?

thank you

Rogerio.

Quartus-II ver.10sp1 not generating programming files for cyclone4GX (EP4CGX22BF14C8?

sk616 — Fri, 18 May 2012 09:10:50 GMT

Hi guru,

I am using Quartus-II version 10.0sp1 for my project using the Cyclone4-GX (EP4CGX22BF14C8) chip. During the full compilation, I notice at the Assembler (Generating Programming Files) stage, there is warning message as below:

Info: Compilation Report contains advance information. Specifications for device EP4CGX22BF14C7 are subject to change. Contact Altera for information on availability. No programming file will be generated.
Warning: No memory initialization file will be produced. The device EP4CGX22BF14C7 only has advanced support.

Also I check the project folder and found that the xxx.SOF and xxx.POF (programming files) are not getting refreshed.

Then I open the Programmer console and use JTAG method to detect the cyclone4GX device on the board, it detects the fpga as unknown fpga. (I tried to detect it using Quartus-II version 11, and it shows up as Cyclone-4GX EP4CGX22BF14C8).

Is that means that the Quartus version10 not supporting this larger 22k logic cyclone4GX? Any of you encounter the same issue and have a solution for this?

I am trying to avoid to use the Quartus version11 for my project as the code is leverage from another legacy project, and it somehow will not function when i use version11 to compile it.

GXB transceiver between two fpgas

mirza — Fri, 18 May 2012 04:23:42 GMT

Hello

I want to establish communication between two fpgas over gxb transcievers. I will use two cyclone iv gx devices. My question is can I send signals from gxb banks (pins) through lvds cable, or does it really need to be a PCIe connector?

Regards

Regarding megafunction cycloneii_crcblock

ptangella42 — Fri, 18 May 2012 01:00:23 GMT

I am trying to access the CycloneII_crc block using the megafunction (cycloneii_crcblock). I have appended my code with this message. The code compiles and synthesize and maps properly. However, when I try to run the timing simulations the output of the crc-block CRC_ERROR, REGOUT, always remain at undefined state. I tried several combinations of shiftnld and ldsrc. I suplied 50MHZ clock in the waveform, I ran the simulation for up to 50ms (which takes about 5mins to run)

Any help will be appreciated.

Thank you in advance.

============my code=================================
module light(a, f, y, x1, x2,CLOCK_50, e, z,);
input a, x1, x2;
input CLOCK_50;
output f, y, z;
output e;
assign f=(x1&~x2)|(~x1&x2);
assign y= ~z;
cycloneii_crcblock XOR_research
(
.clk(CLOCK_50),
.shiftnld(a),
.ldsrc(f),
.crcerror(e),
.regout(z)
);

endmodule

Quartus II Web Edition installation problem on Fedora Core 17

tthtlc — Fri, 18 May 2012 00:41:05 GMT

Installation has a problem:

./11.1sp2_259_quartus_free_linux.sh
Creating directory 11.1sp2_259_quartus_free_linux
Verifying archive integrity... All good.
Uncompressing Quartus II Web Edition (Free)............................................ .................................................. .................................................. .................................................. .
Welcome to Altera Software Installer
Copyright (c) Altera Corporation 2011

Nothing started up, so looking at the trace file as indicated:

Traceback (most recent call last):
File "", line 14, in
File "/tools/python/2.6.4/linux32/pyinstaller/iu.py", line 436, in importHook
File "/tools/python/2.6.4/linux32/pyinstaller/iu.py", line 495, in doimport
File "/tools/python/2.6.4/linux32/pyinstaller/iu.py", line 297, in getmod
File "/tools/python/2.6.4/linux32/pyinstaller/archive.py", line 468, in getmod
File "/tools/python/2.6.4/linux32/pyinstaller/iu.py", line 109, in getmod
ImportError: libXext.so.6: cannot open shared object file: No such file or directory

My System:

FC 17 beta (64-bit) on AMD64-based motherboard. Is 64-bit a problem to install Quartus II web edition?

Problem with Always block

notooth — Fri, 18 May 2012 00:25:42 GMT

I have an Always block that is supposed to run when variable a assigned to 1. But it actually runs anytime when synthesising in Quartus. Can anyone help me resolve it? :confused:

Code:

 module main;

       bit a = 0;

       

       always @ (a==1)

           begin

                 // Run code

           end

 endmodule

Stratix IV PLL limits

vvr108 — Thu, 17 May 2012 21:57:25 GMT

Hi:

I have a 2 fpga stratix iv board and I want to generate a 1 MHz synchronous clock
in both. When I use the PLL, quartus refuses to let me give a clock slower than 5MHz
to the PLL. How can I do this with a PLL?

thanks.

EP600 programming

tfkeel — Thu, 17 May 2012 21:40:33 GMT

I used some of these about 20 years ago. The need has arisen to modify a program (one which I didn't write) and program a handful of chips with the new code.

Can someone tell me if I'm on the right tracks?

I think I can use MAX PLUS+2 for this. Also a program called PLDshell (which I think I used to use). It seems these two programs are easily available. Even though PLD is a dos program (?).

I think there should be folks around who still have programmers supporting this chip. My first approach will be to find someone I can send chips and a file to.

If that fails, second approach will be to buy a used programmer. Does anybody here know which ones support the chip?

Thanks.

Detecting Jtag connection

BillA — Thu, 17 May 2012 20:24:14 GMT

I want to be able to detect if the Jtag USB Blaster is connected, or if it is and connected to the NIOS II debugger. Is there a simple address to read to check for its presence?

I have my own I/O (printf, puts, gets, getchar, etc.) which I direct to Telnet if connected, RS-232 serial otherwise, unless there is a Jtag uart in which case I use it. I use my own Jtag serial code (because it's way more efficient and smaller). I notice Altera code runs a timer and clears the "presence" state if the timer times out and there is no Jtag activity (AC bit in Jtag control). I use my own code because I don't want the alt_alarm and ioctl baggage while still being able to detect if the Jtag is connected.

There has to be a better way than running a timer looking for activity. I set in my Jtag ISR a "JtagPresent" variable but when running in the debugger I don't get an interrupt to set this flag. This would be enough for me to know to use Jtag over the real serial port.

Is there a way using the hardware (not altera driver) to detect if the Jtag is present or not?

Thanks,
Bill

Read program from EP1810LC

Awann — Thu, 17 May 2012 19:07:58 GMT

Hello all, is it possible to read the programming file from an EP1810LC, save it and them use that file to program a different EP1810LC?

We have some old boards that we need to replicate, but the CPLD source code and programming files are whereabouts unknown (it was not our design).

Thanks in advance!