Altera Forums

connection of spi input in de2 board

pearl87 — Mon, 06 Sep 2010 04:31:34 GMT

i am now working on a project and stuck on making a decision whether to use spi input or parallel input using several adc ic's i need to send in 8*3 bits of data in to it which is 24 bits and this need to be comapred before processing which should i used n how to make the connections i am still new with the altera de2 board....

Quartus uses only 4 processors

Angel — Mon, 06 Sep 2010 02:51:44 GMT

In the "What's New in Quartus II Software Version 10.0?" page:
http://www.altera.com/products/softw...whats-new.html

it is said:
"In addition, Quartus II software now supports eight core processors with multiprocessor support, delivering, on average, a more than 20 percent compile time reduction."

When compiling my project on a PC with 12 processors (2x6 core, HyperThreading disabled), the fitter never uses more than 4 processors.

This can be viewed in compile report (getting up to 3.9 averaged processors used) and by watching the Task Manager during fitter operation)
The project is set up for 10 processors.

Using Quartus 10.0 SP1 64-bit program under Windows 7 Ultimate 64-bit.
We have compile times of up to 15 hours and the fitter uses most of the time so it would make a difference.

Kindly help on this.
Thanks
Regards
Angel

Help!!! cfi flash programmer error

lameck — Mon, 06 Sep 2010 01:45:01 GMT

I use nios2-flash-programmer command with argument "--debug" , it shows:
Using cable "USB-Blaster [USB-0]", device 1, instance 0x00
Resetting and pausing target processor: OK
Reading System ID at address 0x00802010: verified
Found CFI table in 16 bit mode
Raw CFI query table read from device:
0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
20: 51 00 52 00 59 00 02 00 00 00 40 00 00 00 00 00 Q.R.Y.....@.....
30: 00 00 00 00 00 00 27 00 36 00 00 00 00 00 07 00 ......'.6.......
40: 07 00 0A 00 00 00 03 00 05 00 04 00 00 00 17 00 ................
CFI query table read from device:
10: 51 52 59 02 00 40 00 00 00 00 00 27 36 00 00 07 QRY..@.....'6...
20: 07 0A 00 03 05 04 00 17 02 00 05 00 02 07 00 20 ...............
30: 00 7E 00 00 01 00 00 00 00 00 00 00 00 00 00 00 .~..............
CFI extended table read from device:
0: 50 52 49 31 33 10 02 01 00 08 00 00 02 B5 C5 02 PRI13...........
10: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
Read autoselect code 0001-007E (in 16 bit mode)
No CFI override data for [FLASH-0001-007E]
Device size is 8MByte
Erase regions are:
offset 0: 8 x 8K
offset 10000: 127 x 64K
Device supports AMD style programming algorithm
Multi-byte programming with 32 byte buffer
Sector erase timeout is 16s
Word program timeout is 1ms
Buffer program timeout is 4ms
: Checksumming existing contents
00000000 : Checksum failed - needs erase then program
00002000 : Checksum failed - needs program
00004000 : Checksum failed - needs program
00006000 : Checksum failed - needs program
00008000 : Checksum failed - needs program
0000A000 : Checksum failed - needs program
0000C000 : Checksum failed - needs program
0000E000 : Checksum failed - needs program
00010000 : Checksum failed - needs program
00000000 : Reading existing contents
Checksums took 0.0s
00000000 ( 0%): Erasing
Erased 8kB in 0.0s
00000000 ( 0%): Programming
Program failed
Leaving target processor paused

and i make a override file "ovet.txt" like this:
[FLASH-0001-007E]
CFI[0x10] = 0x51
CFI[0x11] = 0x52
CFI[0x12] = 0x59
CFI[0x13] = 0x02 # The primary command set, found at CFI table -
CFI[0x14] = 0x00 # addresses 0x13 and 0x14 is overridden to 0x02, 0x00.
CFI[0x15] = 0x04
CFI[0x16] = 0x00
CFI[0x17] = 0x00
CFI[0x18] = 0x00
CFI[0x19] = 0x00
CFI[0x1A] = 0x00
CFI[0x1B] = 0x27
CFI[0x1C] = 0x36
CFI[0x1D] = 0x00
CFI[0x1E] = 0x00
CFI[0x1F] = 0x07
CFI[0x20] = 0x07
CFI[0x21] = 0x0A
CFI[0x22] = 0x00
CFI[0x23] = 0x03
CFI[0x24] = 0x05
CFI[0x25] = 0x04
CFI[0x26] = 0x00
CFI[0x27] = 0x17
CFI[0x28] = 0x01
CFI[0x29] = 0x00
CFI[0x2A] = 0x00
CFI[0x2B] = 0x00
CFI[0x2C] = 0x02 # The number of CFI Erase block regions, found at CFI table �address 0x2C is overridden to 0x1.
CFI[0x2D] = 0x07
CFI[0x2E] = 0x00
CFI[0x2F] = 0x20
CFI[0x30] = 0x00
CFI[0x31] = 0x7E
CFI[0x32] = 0x00
CFI[0x33] = 0x00
CFI[0x34] = 0x01
CFI[0x35] = 0x00
CFI[0x36] = 0x00
CFI[0x37] = 0x00
CFI[0x38] = 0x00
CFI[0x39] = 0x00
CFI[0x3A] = 0x00
CFI[0x3B] = 0x00
CFI[0x3C] = 0x00
CFI[0x40] = 0x50
CFI[0x41] = 0x52
CFI[0x42] = 0x49
CFI[0x43] = 0x31
CFI[0x44] = 0x33
CFI[0x45] = 0x00
CFI[0x46] = 0x02
CFI[0x47] = 0x01
CFI[0x48] = 0x01
CFI[0x49] = 0x04
CFI[0x4A] = 0x00
CFI[0x4B] = 0x00
CFI[0x4C] = 0x01
CFI[0x4D] = 0xB5
CFI[0x4E] = 0xC5
CFI[0x4F] = 0x04
CFI[0x50] = 0x01
CFI[0x51] = 0x00
and i use nios2-flash-programmer command whit arguments --debug --override=over.txt it shows:
# Programming flash with the datafile
"$SOPC_KIT_NIOS2/bin/nios2-flash-programmer" --base=0x00000000 --cable='USB-Blas
ter [USB-0]' --sidp=0x00802010 --id=956946544 --timestamp=1283733585 --instance=
0 -D --override=over.txt "test_flash.flash"
Reading override file "over.txt"
Using cable "USB-Blaster [USB-0]", device 1, instance 0x00
Resetting and pausing target processor: OK
Reading System ID at address 0x00802010: verified
Found CFI table in 16 bit mode
Raw CFI query table read from device:
0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
20: 51 00 52 00 59 00 02 00 00 00 40 00 00 00 00 00 Q.R.Y.....@.....
30: 00 00 00 00 00 00 27 00 36 00 00 00 00 00 07 00 ......'.6.......
40: 07 00 0A 00 00 00 03 00 05 00 04 00 00 00 17 00 ................
CFI query table read from device:
10: 51 52 59 02 00 40 00 00 00 00 00 27 36 00 00 07 QRY..@.....'6...
20: 07 0A 00 03 05 04 00 17 02 00 05 00 02 07 00 20 ...............
30: 00 7E 00 00 01 00 00 00 00 00 00 00 00 00 00 00 .~..............
CFI extended table read from device:
0: 50 52 49 31 33 10 02 01 00 08 00 00 02 B5 C5 02 PRI13...........
10: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
Read autoselect code 0001-007E (in 16 bit mode)
Processing CFI override data from [FLASH-0001-007E]
Override data came from over.txt
Applied override CFI[0x10] = 0x51
Applied override CFI[0x11] = 0x52
Applied override CFI[0x12] = 0x59
Applied override CFI[0x13] = 0x02
Applied override CFI[0x14] = 0x00
Applied override CFI[0x15] = 0x04
Applied override CFI[0x16] = 0x00
Applied override CFI[0x17] = 0x00
Applied override CFI[0x18] = 0x00
Applied override CFI[0x19] = 0x00
Applied override CFI[0x1A] = 0x00
Applied override CFI[0x1B] = 0x27
Applied override CFI[0x1C] = 0x36
Applied override CFI[0x1D] = 0x00
Applied override CFI[0x1E] = 0x00
Applied override CFI[0x1F] = 0x07
Applied override CFI[0x20] = 0x07
Applied override CFI[0x21] = 0x0A
Applied override CFI[0x22] = 0x00
Applied override CFI[0x23] = 0x03
Applied override CFI[0x24] = 0x05
Applied override CFI[0x25] = 0x04
Applied override CFI[0x26] = 0x00
Applied override CFI[0x27] = 0x17
Applied override CFI[0x28] = 0x01
Applied override CFI[0x29] = 0x00
Applied override CFI[0x2A] = 0x00
Applied override CFI[0x2B] = 0x00
Applied override CFI[0x2C] = 0x02
Applied override CFI[0x2D] = 0x07
Applied override CFI[0x2E] = 0x00
Applied override CFI[0x2F] = 0x20
Applied override CFI[0x30] = 0x00
Applied override CFI[0x31] = 0x7E
Applied override CFI[0x32] = 0x00
Applied override CFI[0x33] = 0x00
Applied override CFI[0x34] = 0x01
Applied override CFI[0x35] = 0x00
Applied override CFI[0x36] = 0x00
Applied override CFI[0x37] = 0x00
Applied override CFI[0x38] = 0x00
Applied override CFI[0x39] = 0x00
Applied override CFI[0x3A] = 0x00
Applied override CFI[0x3B] = 0x00
Applied override CFI[0x3C] = 0x00
Applied override CFI[0x40] = 0x50
Applied override CFI[0x41] = 0x52
Applied override CFI[0x42] = 0x49
Applied override CFI[0x43] = 0x31
Applied override CFI[0x44] = 0x33
Applied override CFI[0x45] = 0x00
Applied override CFI[0x46] = 0x02
Applied override CFI[0x47] = 0x01
Applied override CFI[0x48] = 0x01
Applied override CFI[0x49] = 0x04
Applied override CFI[0x4A] = 0x00
Applied override CFI[0x4B] = 0x00
Applied override CFI[0x4C] = 0x01
Applied override CFI[0x4D] = 0xB5
Applied override CFI[0x4E] = 0xC5
Applied override CFI[0x4F] = 0x04
Applied override CFI[0x50] = 0x01
Applied override CFI[0x51] = 0x00
Device size is 8MByte
Erase regions are:
offset 0: 8 x 8K
offset 10000: 127 x 64K
Device supports AMD style programming algorithm
Multi-byte programming not supported
Sector erase timeout is 16s
Word program timeout is 1ms
: Checksumming existing contents
00000000 : Checksum failed - needs erase then program
00002000 : Checksum failed - needs program
00004000 : Checksum failed - needs program
00006000 : Checksum failed - needs program
00008000 : Checksum failed - needs program
0000A000 : Checksum failed - needs program
0000C000 : Checksum failed - needs program
0000E000 : Checksum failed - needs program
00010000 : Checksum failed - needs program
00020000 : Checksum failed - needs program
00030000 : Checksum failed - needs program
00040000 : Checksum failed - needs program
00050000 : Checksum failed - needs program
00060000 : Checksum failed - needs program
00070000 : Checksum failed - needs program
00000000 : Reading existing contents
Checksums took 0.3s
00000000 ( 0%): Erasing
Erased 8kB in 0.0s
00000000 ( 0%): Programming
Program failed
Leaving target processor paused

please help!

Same propagation delay for two signals

mda — Sun, 05 Sep 2010 18:15:38 GMT

Hi,

In my design i am using a combinational function with 2 inputs and four outputs.

The problem is that, when i check the outputs of the FPGA i found glitches that are 'i think' due to a propagation delay that affects the inputs.

How could i tell the FPGA that i want that the propagation delay from PINS to the COMBINATIONAL bloc should be the same : the two signal arrives at the same time ?

Thanks in advance.

Help ERROR: SOPC_KIT_NIOS2 - Undefined variable

MCC — Sun, 05 Sep 2010 17:56:28 GMT

Hi i am a beginner in using nios.I tried to build hello world from nios ide and its giving me the following error

D:/altera/91sp2/quartus/NIOS_DE2/software/Testing_bsp/../../TOP_LV.jdi
ERROR: SOPC_KIT_NIOS2 - Undefined variable
make: *** [Testing.elf] Error 255
make: *** Deleting file `Testing.elf'

i am using quartus/nios ide 9.1 with service pack 2 installed
i have my SOPC_KIT_NIOS2 environent variable set to D:\altera\91\nios2eds
but still i dont understand why its giving me this error. i canot find an altera.components folder in my project explorer window in IDE.It would be great if you guys can give me some suggestions with this issue
(please find the screen shot in the attachment)

Attached Images

IDE.jpg (116.7 KB)

The proble of testbench

li_polaris — Sun, 05 Sep 2010 17:03:37 GMT

Hi!
I am a newbie of the testbench,during the learning I meet some problem.

There is something wrong with the "dataout/=i",maybe they are different type.
what should I do to convert them into the same type?

please help me.

Attached Images

捕获.JPG (40.0 KB)

Attached Files

FX.txt (2.7 KB)

SDRAM problems migrateing neek tutorial to 10.0

Uk Fixer — Sun, 05 Sep 2010 14:53:27 GMT

Hi,
I have tried running SOPC builder on the neek_sopc_builder_hw_tutorial using the latest set of tools, quartus 10.1. I get the following error when I generate;
Error: ddr_sdram: DDR and DDR2 SDRAM controllers in High Performance Controller II architecture only support "Memory burst length" setting of 8 at half rate. Click "Modify Parameters" in "Memory Settings" page to change the "Memory burst length" or change the controller data rate.
Warning: ddr_sdram: Cannot meet tRRD requirement of 0.0 ns. For a Memory interface clock frequency of 150.0 MHz, the minimum is 7.3 ns. Click "Modify Parameters" to change the requirement or adjust the Memory interface clock frequency.

Where am I going wrong and what has changed between 9.0 and 10.1

Thanks

Modling a State Machine in VHDL ... with trouble memorizing variables

carlo_s — Sun, 05 Sep 2010 11:52:22 GMT

Hi,

I'm trying to make a state-machine wich remains in one of the states until one of the variables goes from zero to one three times. I assume it should be quite simple, but after some days I can't succeed. I have tried to save the number of changes both in variables and signals, but no result.

To make a simple test, I just made one simple state-machine with two states. It remains on the first one till the signal_to_monitor =1. Then it goes to second state and the idea is to get out of that state after three transitions 0-1 of the signal we are monitoring.

The code used is:

architecture ctrl_machine of machine is

type possible_states is (first_st,second_st);
signal next_state,state: possibles_states;
signal accumulate : integer range 0 to 5;

begin

RefreshState : process (clk,reset)
begin
if (reset='1') then
estat <= idle;
elsif (clk'event and clk='1') then
estat <= seguent_estat;
end if;
end process RefreshState;

NextState : process (state,signal_to_monitor)

begin
next_state <= state;
case state is

when first_st =>

if (signal_to_monitor ='1') then
next_state <= second_st;
else
accumulate <=0;
next_state <= first_st;
end if;

when second_st =>
next_state <= buidant_calaix;
if (signal_to_monitor = '1') then
accumulate <=accumulate +1;
end if;
if (accumulate = 3) then
next_state<=first_state;
end if;
end case;
end process;

output_proc : process (state)
begin

case (state) is
when first_st => output <='0';
when second_st => output <='1';

end case;
end process ;

(...)

I assume it should be a conceptual error but can't find it! The signal (accumulate) gets mad and begins to flip-flop without control (suppose due to accumulate=accumulate+1 but don't know how to accomplish this simple goal!).

Any ideas?

Thanks!!!

Carlos

Why won't my FIFO Fill?

sebastian.f — Sun, 05 Sep 2010 09:37:31 GMT

Hello,

In my SOPC design I have a Dual Clock FIFO fed by an SGDMA clocked at 80Mhz (no burst) and feeding a video pipeline clocked at 20Mhz.

My SDRAM is 8bit and the SGDMA is clocking out 16bit (2 symbols per beat).

The video sync generator implements backpressure with the 'ready' signal but yet the FIFO will not maintain a consistent level.

Just entering a loop in my program which reads the FIFO CSR I get the following which is usual for what is continually repeated.
(Each entry seperated by a few ms)

It seems as if my FIFO isn't deep enough to successfully buffer the large amount of data that is passing through it (its ~8K deep but thats only 8 lines or so on my display), but at 80Mhz shouldnt my SGDMA be sourcing double what the video pipeline can sink, even without the backpressure from the video sync generator?

Code:

 

FIFO Fill Level: 22 units.

FIFO Fill Level: 0 units.



FIFO Fill Level: 0 units.

FIFO Fill Level: 0 units.

FIFO Fill Level: 36 units.

FIFO Fill Level: 0 units.

FIFO Fill Level: 0 units.

FIFO Fill Level: 9 units.

FIFO Fill Level: 2642 units.

FIFO Fill Level: 0 units.

FIFO Fill Level: 0 units.

FIFO Fill Level: 0 units.

FIFO Fill Level: 24 units.

FIFO Fill Level: 0 units.

FIFO Fill Level: 0 units.

FIFO Fill Level: 5 units.

FIFO Fill Level: 30 units.

FIFO Fill Level: 14 units.

FIFO Fill Level: 0 units.

FIFO Fill Level: 14 units.

FIFO Fill Level: 24 units.

FIFO Fill Level: 0 units.

FIFO Fill Level: 0 units.

FIFO Fill Level: 40 units.

FIFO Fill Level: 0 units.

FIFO Fill Level: 0 units.

FIFO Fill Level: 0 units.

Qpsk Modem

slindsay — Sat, 04 Sep 2010 19:43:29 GMT

Which of the development kits can I purchase to implement the QPSK modem REFERENCE DESIGN as described in the october 2003 reference document.

quartus 10 wont generate sof file

dabaf — Sat, 04 Sep 2010 19:05:46 GMT

Hi everybody,

I have a serious problem concerning generating sof file using Quartus 10. I am using a DE2 BOARD(CYCLONE EP2C35 ) and when I compile my project everything is fine, but it wont generate the sof file so I can program my DE2 BAORD. by the way I download the quartus 10 from ALTERA website.

any help will be very appreciated.

David,

Embedded compilation by Python scripts

info.reembedded — Sat, 04 Sep 2010 17:19:29 GMT

I would like to share a link to short article or news about scripting embedded software by python script.

reembedded.com/index.php?option=com_content&view=article&id=73:em bedded-compilation-by-python-scripts&catid=50:latest-embedded-news&Itemid=115&lang=en

DDR2 SDRAM interleving??

sberyilmaz — Sat, 04 Sep 2010 16:48:13 GMT

Hi everyone,

I am using Cyclone III dev. board. I am trying to design a DDR2 SDRAM controller using SOPC builder. I need to increase the bandwidth and want to do memory interleaving, but have no idea how to do that. Is there a setting in SOPC DDR2 wizard to do interleaving, or do I have to write it myself?

How to simulate FPGA configration?

cyberholic — Sat, 04 Sep 2010 12:02:14 GMT

:confused: :confused: :confused: How to simulate FPGA configration?

No filesystem could mount root

yingfang18 — Sat, 04 Sep 2010 11:24:54 GMT

hello:
I was trying to transplant uClinux to DE2 for two weeks,I follow the wiki step by step!
and the error message is:
Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)

After I found a lot of web page.I found the mistake was happen at romfs,because,when I do the order "make romfs",it says "nothing to do for romfs",and the romfs file is empty.
When I follow this web page,http://www.nioswiki.com/index.php?ti...ight=initramfs
I delete the romfs and make it again,the results is the same!
I think the problem is the rootfs,but I don't know how to resolve it.
I was using Ubuntu 9.10,quartus and IDE 8.1,and the uClinux-dist is uClinux-dist-20070130.tar.gz,and the my NiosII gcc cross compiler is nios2gcc-20080203,and it is successfull.
I have confused it for a few weeks,but I still resolve the problem,please tell me how to do,how to build the rootfs or how to transplant uClinux to DE2.Thank you very much!

Quartus II on NetBook Computer w/Win7 starter OpS

ELI_HAIT — Sat, 04 Sep 2010 08:27:26 GMT

hi, folks,
i am a sub-contractor designer, and from tome to time a have to come to customer lab for system debug & integration.
i am tired of running around with large 15", multi-kilogram, high performance laptop computer.....

i'm thinking of option to buy a high-screen-resolution netbook computer, like lenovo idealpad d10-3 and use it in 2 modes:

for light fpga designs i want the Quartus II to be installed on the netbook and run from it. the netbook is quite limited - it's usually equipped with atom N450 processor, 1G memory and has Win7 starter for operating system.
1. would the quartus II run on this kind of machine and operating system? 2. would the run times be reasonable for instance to run compile design on EP3C16, 70% utilization?

the other way, for really "heavy" designs, i want to run the whole thing via remote desktop application (like LogMeIn) on server in the office and use the netbook to program the device on target by usb-blaster and to use the signal tap interface.
1. the signal tap is an iterative application. do you think the netbook is strong enough to support this kind of operation?

does anyone has such experience? any advice?
is there any special support by quartus II software i should know?

thanx in advance
eli.

TSE can't be softreset.what' the promble?

wgwen — Sat, 04 Sep 2010 03:09:34 GMT

Hi ,guys!
I set the SW_RESET bit of command_config register to 1 in the hope of reset the TSE.But this bit is always 1,it isn't automatically cleard!Can anybody tell me why?I'll apprecate for your help!

DE2 70 CRC Error

Wilsoneto — Fri, 03 Sep 2010 19:03:59 GMT

Hi, I have a problem in load uclinux in my DE2 70, i try to use the TryOutuclinux( the .sof and zImage downloaded of the wiki page) but the frist problem was when I maked the line command 'nios2-configure-sof' I received this error :

ERROR: File DE2_70_NIOS_HOST_MOUSE_VGA.sof is corrupted

After I take this file on my DE-2 CD and the command work fine, after I maked 'nios2-download -g zImage' , and work fine too, but when I do 'nios2-terminal' I received this error:

"Uncompressing Linux...
ERROR
crc error"

what you thing? its necessary use the .sof file of the wiki page? i don't thing this because the file of DE2 CD its the same. maybe my zImage file is corrupted too? help me please.

DE1 Demonstrations, problem with VGA and TOOLS � Multi-Port SRAM/SDRAM/Flash Controll

johnpre — Fri, 03 Sep 2010 17:29:33 GMT

Hi,

I cannot have the VGA demonstrations correctly working.

I can see the default image and the cursors, but if I try to use any else image created by the image converter (.dat, .txt ecc...) and load the file into SRAM and then configure the asynchronous port1 (also tried the other ports!) no correct imagers are shown; actually, only the created .txt file shows some portions of the image, but not correctly.

Anyone have the same problem?

Tx
John

A minimal "from scratch" on your own hardware example?

davidsmoot — Fri, 03 Sep 2010 16:42:32 GMT

Short version of the question:
Where can I find a tutorial on starting from custom hardware to getting the most basic "hello world" NIOS running?

Long version of the question:

I'm probably one good Google search away from what I want but I can't seem to find it.

I have a Cyclone II based board we built in house. The board is up and running and doing useful non-processor things. When we were laying out the board hardware, we knew we probably wanted some kind of soft processor. At the time, we were using the FPGA tools built into Altium so we copied the SDRAM, flash, and SRAM hardware from the Altium "Nanoboard 2000" (had to remove the link since this is my first post). I've gotten our hardware to run the simple webserver examples from Altium so I know the hardware is good.

In the time since we laid out the hardware and now, we've migrated to native Quartus tools for our behavioral VHDL for the better test and debug capabilities. Now I want to instantiate a NIOS based soft processor in our hardware to make sure that the hardware is compatible with the NIOS environment.

So what I am trying to do is start with a minimal NIOS system with just on-chip RAM and a JTAG UART and get a "hello world" going. If I can do that, then I can add my hardware components one at a time and test. But I keep running into simple problems. All the examples I can find assume you have working and known good hardware and BSP. I want an example of creating a BSP from scratch to test hardware. Any suggestions?

David

Edit: Murphy's law, you always find what you are looking for right after you post a detailed question on the forum. I think this is what I am loooking for altera.com/literature/tt/tt_nios2_hardware_tutorial.pdf