[Hey_Hey]

Another suggestion, when setting USE_RCSLAVE to 1 and trying to Write and Read from BAR0, use an offset above 32 (and less than 32KB) when accessing it. That should be some just plain old Read/Write memory. Offsets 0-31 from BAR0 have some undocumented internal testing features.

[likewise]

Hello,

in first instance I would like to mimick what the testbench does, when starting a device driver. I am reading PCIe Compiler 8.0 UG, May 2008.

Page 7-16 describes the Test Module:

the Descriptor Header for write DMA is at 0x00-0x10, and for reads is at 0x10-x20. In the Descriptor Header, the base address descriptor fields is set to 0x800.

However, the first Descriptor is placed at 0x810, the next at 0x820, etc.

Now, my question is, what must be at 0x800??

The only reference to 0x800, is page 7-18 where it is said that at 0x80c the DMA engine is writing its completed DMA number.

My suspicion is that at 0x800 a copy of the header must be, which is written by the DMA engine and where EPLAST is written.

Any ideas?

Regards, Leon.

[johan_s]

Ok we found the problem. We were reseting only the dma read (the only we use) and we need to reset the dma write to !!! and that working fine

[johan_s]

The last problem we have is that using chainning dma exmemple in verilog the every thing is ok when it is generated in VHDL dma transfers are halted ?!? using the same pc driver and api : (
any ideas ?

[likewise]

I have published a Linux device driver:

http://marc.info/?l=linux-kernel&m=122813921631142&w=2

[BrettFavre]

I am having some difficulty generating multiple DMA transfers in the chaining DMA design example that is used in the PCI Express high performance reference design. After looking through the RTL, it appears to me that I must perform the following sequence prior to initiating a new transfer:

[1] write the value 0x0000ffff to the control register DW0 (either read or write depending on the desired transfer) prior to initiating a new transfer
[2] setup DW0, DW1, DW2, and DW3 with desired transfer parameters
[3] be sure to write DW3 last as writing DW3 puts the DMA engine in motion

From what I can tell, step[1] is required for each descriptor table that describes a transfer. Without step [1], it appears that a write to DW3 will not initiate a new transfer.

There have been a few comments in this thread that seem to support this. However, I wanted to spell it out in detail and get clarification. Can anyone comment?