[BrettFavre]

I am having some difficulty generating multiple DMA transfers in the chaining DMA design example that is used in the PCI Express high performance reference design. After looking through the RTL, it appears to me that I must perform the following sequence prior to initiating a new transfer:

[1] write the value 0x0000ffff to the control register DW0 (either read or write depending on the desired transfer) prior to initiating a new transfer
[2] setup DW0, DW1, DW2, and DW3 with desired transfer parameters
[3] be sure to write DW3 last as writing DW3 puts the DMA engine in motion

From what I can tell, step[1] is required for each descriptor table that describes a transfer. Without step [1], it appears that a write to DW3 will not initiate a new transfer.

There have been a few comments in this thread that seem to support this. However, I wanted to spell it out in detail and get clarification. Can anyone comment?